The CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI

Express with the well-proven X-Cell™ architecture, to provide industry leading performance

using the UMC standard eight-metal 0.13-μm deep submicron process. Only two to four metal

layers are used for customization, allowing prototypes to be manufactured, assembled, tested,

and shipped in just 4 to 5 weeks.

The built-in, silicon-proven PCI Express PHY, in combination with the ChipX synthesizable

processors and PCI Express endpoint, root port, or bridge controllers, form a complete PCI

Express subsystem capable of achieving PCI-SIG compliance. You can also use your own PCI

Express controller where desired. The PCI Express subsystem on the CX6100 family of products

removes complexity and the risk of IP selection and IP interoperability testing.

The CX6100 product family builds on four generations of ChipX Structured ASIC products (see

Table 1). The core technology combines our accumulated design expertise with a focus on

Networking and Industrial PCI Express interface needs. The CX6100 PCI Express Structured

ASIC platform delivers an ideal solution that is high performance and appropriate for low to

high-volume production.

Applications

The CX6100 is optimized with IP content and size ranges to support specific system

applications.

Table 1 CX6100 SerDes/PCI Express Structured ASIC Platforms

Part

Number1

1. ChipX will consider a private product for your company.

Usable

Gates

(KGates)

Memory

(Kbits)

(9-Kb

Banks)

Cache

Memory

Blocks

PLL

Maximum

Configurable

I/O2

2. Configurable I/O excludes PCI Express PHY pins and Power/Gnd connections

PCIe

Lanes Packages

CX6104 350 360 (40) — 4 138 4 256 LBGA

CX6106 400 324 (36) — 4 146 4 256 LBGA

CX6112 450 288 (32) — 4 156 4 256 LBGA

CX6113 765 880 (97) 16KB, 16KB 4 210 4

456 PBGA,

676 PBGA

CX6115 680 990 (110) 16KB, 16KB 4 235 4

CX6119 595 1100 (122) 16KB, 16KB 4 252 4

CX6142 1330 1800 (200) 16KB, 16KB 4 290 8

CX6146 1520 1620 (180) 16KB, 16KB 4 312 8

CX6149 1710 1440 (160) 16KB, 16KB 4 336 8

2 of 2 0289-6k-070-C January 17, 2008

CX6100 ChipX Product Brief

Structured ASIC with PCI Express

Design Flow

ChipX spends considerable development effort to ensure that taping out a design to a CX6100

Structured ASIC is simple, painless, and low risk. ChipX provides libraries for Magma, Synopsys,

and Synplicity ASIC synthesis tools.

RTL, ASIC Netlist, or FPGA Netlist Handoff

Many customers prefer to hand off their RTL designs early and let ChipX perform the entire

timing closure loop, including synthesis and final simulations. Our integrated development tools

allow faster overall design cycle with an RTL handoff. ChipX can also rapidly and reliably convert

obsolete design netlists into prototypes.

  Key Features and Benefits

 PCI Express v1.1 PHY offers 2.5-Gbps operation, in four lanes, and 1 x 4, 4 x 1, 1 x 8 or

Tutorials

1.Embedded USB - a brief tutorial

The Standards

USB 1.1

The original USB standard provides a fast Master/Slave interface using a tiered star topology supporting up to 127 devices with up to 6 tiers (hubs). A PC is normally the master or Host and each of the peripherals linked to it act as slaves or Devices.  One of the aims of the design was to minimise the complexity of the Devices by doing as much in the Host as possible. Data transfer rates are defined in the specification as - Low Speed 1.5 Mbits/sec and Full Speed 12 Mbits/sec and the maximum length of each cable section is 5 metres. The USB specification allows each device to take up to 500mA of power (limited to 100mA during startup).

USB 2.0

There are some minor variations from USB 1.1 within the USB 2.0 specification and since USB 2.0s inception most interfaces have been designed to conform to the USB 2.0 standard. The 2.0 specification is a superset of 1.1 and the major functional difference which is the addition of a High Speed 480 Mbits/sec data transfer mode.  Be warned, however, that the Spec does allow a product (eg an interface chip) to say that it is “USB 2.0 compatible” without necessarily implying that it  actually implements the High Speed mode.

USB 3.0

Still at the design stage the 3.0 specification is due out in mid 2008 with products hitting the shops in 2009.  It is being designed to be backward compatible with 2.0 and to add a Super Speed >4.8 Gbits/sec data transfer mode.

2.USB ON-THE-GO: A TUTORIAL

3.A Technical Introduction to USB 2.0

USB PHY and Integration

Many ASIC technologies and architectures have been developed in the past 30 years.  The following are the most well-known ASIC types used in the industry: Standard Cell, Structured ASIC, Hybrid ASIC , Gate Array, Embedded Array.

Standard Cell

standard-cell

Structured ASIC 

structured-asic

 
Hybrid ASICs

hybrid-asic

 Gate Array

Gate Array

The Gate Array is made up of “basic cells,” each cell containing some number of transistors and resistors. Using a cell library (gates, registers, etc.) and a macro library (more complex functions), the customer designs the chip, and ChipX industry standard software tools generate the interconnection masks. Some cells go wasted on Gate Array designs, which is the penalty for being able to benefit from fewer masks to build a chip. This technology has been rendered obsolete with the existence of Structured ASICs.

Embedded Array

Embedded Array

Applications Specific Integrated Circuits or ASICs are, as the name indicates, non-standard integrated circuits that have been designed for a specific use or application. Generally an ASIC design will be undertaken for a product that will have a large production run, and the ASIC may contain a very large part of the electronics needed on a single integrated circuit. As may be imagined, the cost of an ASIC design is high, and therefore they tend to be reserved for high volume products.

Despite the cost of an ASIC design, ASICs can be very cost effective for many applications where volumes are high. It is possible to tailor the ASIC design to meet the exact requirement for the product and using an ASIC can mean that much of the overall design can be contained in one integrated circuit and the number of additional components can be significantly reduced. As a result they are widely used in high volume products like cell phones or other similar applications, often for consumer products where volumes are higher, or for business products that are widely used.

The first Application Specific Integrated Circuits (ASICs) traditionally addressed only logic functions. Now mixed signal ASIC designs can incorporate both analogue (including RF) and logic functions. These mixed signal ASICs are particularly useful in being able to make a complete system on chip, SoC. Here a complete system or product is integrated onto a chip and virtually no other components are required. This makes a mixed signal ASIC design a very attractive proposition for many applications.

ASIC Beginnings

The beginnings of the ASIC can be traced back to the early 1980s. Around this time, ICs were beginning to make a major impact on the electronics industry. In view of the advantages that ICs provided, and the limited number that were available, some attempts were made to create a logic chips that could be easily focussed towards a specific application. One early initiative undertaken by Ferranti, a UK based company, used what was termed the uncommitted logic array (ULA). This scheme provided the customisation by varying the metal interconnect mask.

The first ULAs contained only a few thousand gates, but later versions had greater levels of flexibility and used different base dies customised by both metal and polysilicon layers. In some cases RAM elements were incorporated into the basic ULA.

From these early developments, a number of different types of ASIC have been developed. Now many ASICs are very complicated, and some are mixed signal ASICs that incorporate both analogue and digital circuitry.

ASIC basics

The development and manufacture of an ASIC design including the ASIC layout is a very expensive process. In order to reduce the costs, there are different levels of customisation that can be used. These can enable costs to be reduced for designs where large levels of customisation of the ASIC are not required. Essentially there are three levels of ASIC that can be used:

· Gate Array This type of ASIC is the least customisable. Here the silicon layers are standard but the metallisation layers allowing the interconnections between different areas on the chip are customisable. This type of ASIC is ideal where a large number of standard functions are required which can be connected in a particular manner to meet the given requirement.

· Standard cell For this type of ASIC, the mask is a custom design, but the silicon is made up from library components. This gives a high degree of flexibility, provided that standard functions are able to meet the requirements.

· Full custom design This type of ASIC is the most flexible because it involves the design of the ASIC down to transistor level. The ASIC layout can be tailored to the exact requirements of the circuit. While it gives the highest degree of flexibility, the costs are very much higher and it takes much longer to develop. The risks are also higher as the whole design is untested and not built up from library elements that have been used before.

ASIC design and development stages

There are several stages in an Application Specific Integrated Circuit, ASIC design. Each must be undertaken correctly because errors later in the process become progressively more costly to correct. Ideally the development process should incorporate all the required stages, and each one should be completed satisfactorily before moving on to the next. Often an external specialist company is used to provide the ASIC design service. Accordingly it is necessary to ensure that the interface to the ASIC design service or company is fully functional. One way of doing this is to ensure that the ASIC design process is correct.

Requirements capture In just the same way that capturing the requirements is an essential part of any systems design, the same is true of an ASIC design. It is essential that all the requirements are captured so that the design can be set in place correctly. Changes to the requirements at a later stage will result in design changes that will cost a significant amount to implement.

Modelling At this stage of the ASIC development it is necessary to model the high level functionality of the ASIC design to ensure that the correct approach has been taken. This modelling is normally done in software, often in C or a similar language. In some circumstances it is possible to import the circuit block diagram into the design tool to enable the ASIC modelling to be undertaken.

One very important area of the ASIC modelling at this stage is to ensure that the truncation and rounding elements are incorporated correctly. Any mismatch can create large problems later in the design that can be difficult to locate and correct.

ASIC package selection The choice of package for the ASIC is governed by a number of factors. Obviously the number of connections required has a major influence, but so does the anticipated heat dissipation. Higher levels of heat dissipation will require a package that can transfer the heat from the silicon very effectively. In addition to this the anticipated manufacturing process for the circuit into which the ASIC is to be incorporated will also have an impact. Finally the vendor of the ASIC silicon will affect the choice of package. Different ASIC vendors will offer different packages. Accordingly the final choice will be a balance between all the requirements.

The available packages for ASICs can be chosen from a number of the familiar packages used for large scale integrated circuits and include:

· Quad flat pack (QFP) - although once popular and providing a high level of connectivity, these packages are not robust and are easily damaged. The pins are easily bent prior to soldering onto the target board and as a result very careful handling is required.

· Ball grid array (BGA) - this is often the preferred solution now as BGAs are robust and can be handled in most SMT manufacturing processes.

ASIC design capture The design capture for the ASIC can be achieved in a number of ways. Once of the most obvious methods is to capture the ASIC design from a schematic. This method has been superseded and the designs are normally designed using design tools that capture the mathematical operations required and convert this into the required circuitry representation. There are a number of tools that can perform this including VHDL design tools and Verilog. These tools can control the design at both the high or low level of the design. This enables control of the ASIC design down to the register by register or even the bit by bit level.

ASIC layout

The ASIC layout is an important stage in the development. The level of customisation of the ASIC layout will depend upon the type of ASIC being used, but for full customised designs, the ASIC layout is far more flexible than for the other versions where it may not be possible to determine large elements of the layout.

The ASIC layout will involve many factors from the most convenient proximity of certain sections of the circuit and transit times, to the number of interconnections that need to be made between different areas. The ASIC layout is normally undertaken under computer control, but is nevertheless possible to place restrictions on the ASIC layout to ensure that certain electrical parameters are met.

ASIC simulation and comparison with modelling Once the design of the ASIC has been captured, it is necessary to ensure that the design will meet its requirements and that it will work correctly. Further simulation is undertaken to achieve this. The ASIC design is checked against the software model generated previously. It is found that many of the errors discovered in the final integrated circuit are functional errors that could often be found at this stages if the modelling is a realistic representation of the target or required ASIC functionality. Additionally a careful check of the timing is essential, especially for full custom ASIC designs. This needs to be performed over slightly more than the specified temperature range, the power supply input range and the envisaged process variation.

Formal verification This area of the ASIC design lifecycle has become increasing important in recent years. With the growing complexity of ASIC designs, it has become more important to undertake a formal verification to ensure that the design is correct. Aspects including checks to ensure that all the variables within the software model are correctly defined, as well as checking for aspects such as clock skew, and metastability between different clocked areas of the ASIC design. The metastability is a problem that occurs when data changes at the same instant as the clock. It is the probability versus time to settle of the output data not settling to the required state if the input data and clock change at the same time.

ASIC test techniques Once manufactured, it is necessary to be able to test the ASIC device. Three techniques are normally considered for use. The first is boundary scan, JTAG, IEEE1149.1. Using this technique it is possible to check the input/output areas, and also the internal circuitry within the device. However boundary scan is a serial technique and it is too slow to check much of a complex device.

The second technique uses what are termed scan chains. This technique uses the existing registers from the ASIC, but each one incorporates a multiplexer between the scan input and the normal input. A number of chains can be set up, each having two inputs and an output chain. Test vectors are generated for the inputs and using these it is then possible to analyse the output and detect any errors. Automated scan chain input sequences can be generated and optimised to test all the logic between the registers to check for nodes that may be stuck in a particular state, i.e. 1 or 0.

To speed the ASIC test process a number of chains can be implemented, thereby enabling parallel testing to be accomplished.

Additionally BIST (Built In Self Test) may be used. This is particularly useful in situations such as the test of chips incorporating elements such as SRAM which take a long time to check. Often vendors sell what are termed “canned vectors” for the test of such elements. As these are very cost effective in terms of silicon area and test time. The technique and extent of these vectors can often influence the choice of vendor.

Physical test of prototype ASICs When the physical prototype silicon ASICs are available it is necessary to give them a complete test, including a test with the ASIC in the target circuit. Not only is it necessary to check their operation, but in addition to this, checks of the process spread are undertaken to give an indication of the likely yield in production. The aim is a narrow spread that is not close to pass fail limit edges.

It is possible that some problems will be found at this stage. To investigate the problems a number of techniques can be used. Boundary scan is one powerful tool, and checks can also be made around the interface to the external circuitry. One technique that was used successfully was to probe directly onto the ASIC silicon itself. This is not normally possible now in view of the very small feature sizes that are commonplace today.

Another techniques is to investigate the symptoms and then generate a hypothesis that can then be tested against the simulation of the ASIC. This enables the correct problem to be simulated and then corrected.

Lifecycle reviews & handover to manufacture As with any interface between departments or different areas of a development team it is necessary to ensure that the interfaces operate satisfactorily, and that all the required information is passed over accurately. This is particularly true of the interface with the silicon vendor as they form a different company and will have different processes by which they work. To achieve this, the handover of information to and from the ASIC design service is normally done on a formal basis, and the silicon vendors will often expect to see many items including the verification results for the ASIC design, as part of this.

Summary

ASIC designs offer a very attractive solution for many high volume applications. They enable significant amounts of circuitry to be incorporated onto a single chip. Had the circuits been assembled using proprietary chips, additional components, and hence board area would be needed. Manufacturing costs would be more. With sufficient volume, custom chips, in the form of ASICs offer a very attractive proposition. In addition to the cost aspects, ASICs may also be used sometimes because the enable circuits to be made that might not be technically viable using other technologies. They may offer speed, and performance that would not be possible is discrete components were used. When developing an ASIC, it is often necessary to employ another specialist company to provide the ASIC design service. By using their expertise the design can be undertaken more effectively - in terms of correct functionality, cost and timescale.

ChipX Structured ASICs are optimized for flexibility and fast time to market. They are also targeted at customers seeking an ASIC with a very low NRE. ChipX Structured ASICs combine built-in, silicon proven, industry standard configurable I/Os, memories and mixed signal IP with ChipX’s well-proven L-Cell and X-Cell™ configurable logic cells to provide industry leading performance using technology ranging from 5V in 0.6µ process through advanced processes. Certain product families serve as platforms with pre-integrated and validated high-speed Phy interfaces and firm high-speed DDR and DDR2 memory interfaces.

Features and Benefits

• Product families in 0.13u HS, 0.18u, 0.25u and 0.35u
• Pre-built configurable logic, memory and I/Os enable fast design implementations and rapid fabrication of the top layers of metal only.
• Re-spins and derivatives can be implemented quickly with re-synthesis and no time-consuming and risky ECOs.
• Up to 250 MHz maximum global operating frequency with greater than 20 levels of logic, 1 GHz local
• True ASIC gate count of up to 2M usable gates using ChipX’s fine grain Structured ASIC logic fabric
• High speed, configurable embedded SRAM up to 2 Mbits. SRAM can be configured as single port, dual port or FIFO.
• DDR PHY up to 500Mbps
• 1.2V to 5V core operating voltages
• Wide range of I/O options, including LVTTL, LVCMOS, HSTL, SSTL (18/2/3), LVDS (up to 840 Mbps), RSDS, PCI, PCI-X, XOSC, and others
• Commercial and Industrial grade temperature libraries. Military grade products are also available.
• Built-in configurable PLLs with Spread Spectrum tracking and output range of 10 MHz – 1 GHz
• Multiple DLLs with output frequency of up to 400 MHz can be placed in the logic area
• Packages from 40 QFN to 896 PBGA

	Process	Usable Gates	Total Pads	Max System Clock (MHz)	5V Support	Core Voltage	Max Embedded Memory [K bits]	USB 2.0	PCI/ PCIX/ PCIe	PLL
	0.13µ	140K to 658K	120-200*	250		1.2	216-324	Device, OTG	PCI, PCI-X	4
CX6100	0.13µ	350K-1.7M	138-336**	250		1.2	288-1800	FS	PCI, PCI-X, PCIe	4
CX5000	0.18µ	90K-578K	256-768	200		1.8	160-1264	FS	PCI, PCI-X	4
CX4000	0.25µ	20K to 550K	128-1024	150		1.8/2.5	0-448	FS	PCI, PCI-X	4
CX3000	0.35µ	21K to 200K	125-512	50	√	3.3/5	24-352		PCI (3V/5V)	4

* excluding USB 2.0 PHY pads
** excluding PHY pads

ASIC DESIGN FLOW